This application describes a modified industrial process for LSI manufacturing. One of the major issues today in manufacturing LSI such as ASIC (application specific integrated circuit) or SOC (system-on-a-chip) is a standstill of a production process in the prototype test. More than 50% ICs coming out of the prototype fabrication stage fail to pass the test, which results in suspension of the production process to the next stage (ex. application development and mass production). Within the context of this application, such a situation is called prototype-hold or proto-hold.
When the first silicon (prototype LSI) comes out of fabrication, in majority of cases, it shows some failures in the prototype evaluation. The cause of these failures varies; it can be an error in vector translation (test data conversion), or an error in a test program or even fabrication defects. In a large number of cases, the cause of failure is not easily identifiable and hence, the silicon (prototype LSI) is put on prototype hold (proto-hold). Until the cause is identified and rectified, the silicon cannot be used for application development and subsequently it cannot go into volume production.
The primary factor behind this issue is that the design environment is different from the test-engineering environment and therefore, the cause of failure is not easily identified. When a chip is taped-out (design data of the chip is released from the design engineer), a test engineer is required to convert the design-simulation vectors for use in the test-engineering environment. The test-engineering environment is usually in a cyclized format according to tester time-sets and wave-groups. The test engineer further translates the vectors into another format such as STIL (Standard Test Interface Language) or WGL (Waveform Generation Language) unique to a particular test system and creates a test program that has almost no resemblance to the original simulation. Hence, when the first silicon (prototype LSI chip) shows a failure (failing vector in the test vectors), it is quite cumbersome to determine the cause of the failure.
The semiconductor industry involves extremely expensive and large scale production facilities and a production volume of each LSI device is large. Thus, such a delay caused by the proto-hold is extremely costly for application developers, the design house (ASIC house or design center) as well as for the silicon foundry (semiconductor manufacture). Therefore, there is an urgent need in the industry for a new semiconductor manufacturing process and test system that operate in the IC design environment and eliminate all the complexity involved in the test data conversion into cyclized form as it is done by the present day test systems.